1. Field of the Invention
The present invention relates to a test key formed on a wafer, and more specifically, to a test key for checking the contacting status of a probe card.
2. Description of the Prior Art
In semiconductor fabrication, a semiconductor device or an integrated circuit (IC) is continuously tested in every step so as to maintain device quality. Normally a testing circuit is simultaneously fabricated with an actual device so that the quality of the actual device is judged by the performance of the testing circuit. The quality of the actual device therefore is well controlled.
A typical method to test a wafer is called a wafer acceptance testing (WAT) method, which can measure defects in a wafer. The WAT method includes providing several test keys distributed in a periphery region of a die that is to be tested. The test keys typically are formed on a scribe line between dies, and are electrically coupled to an external terminal through a metal pad. A module of the test keys is selected and each test key off the selected module is respectively used for a test of different property of the wafer, such as threshold voltage (VT) or saturate current (IDSAT). A controlled bias is applied to the test keys, and the induced current is read out to detect defects on the wafer.
When using the test keys to measure the defects of the dies, a probe card with a plurality probes is used to contact with the contacting pads of the test keys so as to proceed the measurement. However, if the probes of the probe card do not properly contact with the contacting pads of the test keys when proceeding the measurement, the real characteristics of the test keys can be known according to the result of the measurement, and then the defects of the dies are hard to be detected. Therefore, when a WAT test proceeding, how to make sure that all of the probes of the probe card are properly contacted with the contacting pads of the test keys is an important issue.